![]() If you specify the +transport_int_delays plus option, a SITD is placed on the destination port.įigure B-6 Output (lower) -> Inout (lower) Any Number of Drivers +multisource_int_delays plus option and all destination loads are accelerated, then a MITD is placed on the net and the delay is annotated from all sources in the source module to the destination. If you specify the +transport_int_delays plus option, a SITD is placed on the destination port.įigure B-5 Output (lower) -> Inout (lower) Multiple Drivers MITD is placed on the net and the delay is annotated from all sources in the source module to the destination. ![]() +multisource_int_delays plus option and all destination loads are accelerated, then a +multisource_int_delays or +transport_int_delays plus option. However, if you specify the +transport_int_delays plus option, then SITD is placed on the net.įigure B-2 Output (lower) -> Input (lower) with XL Fanout Multiple DriversĪ MIPD is placed on the destination port unless you specify the Valid and Invalid Interconnect Combinationsįigure B-1 Output (lower) -> Input (lower) with XL Fanout Single DriverĪ MIPD is placed on the destination port. The following table shows the valid interconnect combinations. The following sections describe the valid and invalid interconnect combinations. In addition, certain combinations of ports may be handled in different manners. When annotating interconnect delays, only certain combinations of ports are allowed by the SDF Annotator. This appendix lists the valid combinations of source and destination ports and the manner in which the SDF Annotator performs the action for each valid combination. ■ Invalid Interconnect Combinations on page 115 Overview ■ Valid Interconnect Combinations on page 102 You specified an output port in a PORT construct. ![]() There is no corresponding CELLTYPE to a CELL that You specified a timing check that does not exist in a WIDTH You specified a timing check that does not exist in a SKEW You specified a timing check that does not exist in a SETUP You specified a timing check that does not exist in a You specified a timing check that does not exist in a HOLD You specified a path that does not exist in the IOPATH TIMESCALE Keyword Restriction in SDF File Header.COND Keyword Matching Condition Restriction.PATHPULSE Limitation for Interconnect Delays.Reverting to Original Timing Limitation.Working with Verilog-XL SDF Annotator Restrictions.Removing Zero-Delay MIPDs, MITDs, and SITDs.Disabling Multisource Interconnect Timing Resolution.Improving SDF Annotator Performance and Memory Use.Additional Plus Options that Control the SDF Annotator.+sdf_split_two_timing_check +sdf_splitvlog_splitsuh +sdf_splitvlog_splitrecrem. ![]() ![]()
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